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MC74HC194 Ver la hoja de datos (PDF) - Motorola => Freescale

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MC74HC194
Motorola
Motorola => Freescale Motorola
MC74HC194 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Bidirectional
Universal Shift Register
High–Performance Silicon–Gate CMOS
The MC74HC194 is identical in pinout to the LS194 and the MC14194B
metal gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pull–up resistors, they are compatible with LSTTL
outputs.
This static shift register features parallel load, serial load (shift right and
shift left), hold, and reset modes of operation. These modes are tabulated in
the Function Table, and further explanation can be found in the Pin
Description section.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity 164 FETs or 41 Equivalent Gates
LOGIC DIAGRAM
SERIAL SA 2
DATA
INPUTS SD 7
A3
PARALLEL
DATA
INPUTS
B4
C5
D6
CLOCK 11
MODE S1
SELECT S0
RESET
10
9
1
15 QA
14 QB
13 QC
12 QD
PARALLEL
DATA
OUTPUTS
VCC = PIN 16
GND = PIN 8
MC74HC194
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC74HCXXXN
Plastic
PIN ASSIGNMENT
RESET 1
SA 2
A3
B4
C5
D6
SD 7
GND 8
16 VCC
15 QA
14 QB
13 QC
12 QD
11 CLOCK
10 S1
9 S0
FUNCTION TABLE
Inputs
Mode
Serial
Select
Data
Parallel Data
Outputs
Operating
Reset S1 S0 Clock SD SA A B C D QA QB QC QD
Mode
L
XX
X
XXXXXX
L
L
L
L Reset
H
HH
XXa b c d
a
b
c
d Parallel Load
H
LH
H
LH
XHX X X X
XLXXXX
H
L
QAn
QAn
QBn
QBn
QCn
QCn
Shift Right
H
HL
H
HL
H X X X X X QBn QCn QDn
L X X X X X QBn QCn QDn
H
L
Shift Left
H
LL
X
XXXXXX
H
XX
L
XXXXXX
H
XX
H
XXXXXX
No Change
No Change
No Change
Hold
H = high level (steady state)
L = low level (steady state)
X = don’t care
= transition from low to high level.
a, b, c, d = the level of steady–state input at inputs A, B, C, or D, respectively.
QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD, respectively, before
the most recent transition of the clock.
10/95
© Motorola, Inc. 1995
1
REV 6

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