MC74HC194 Ver la hoja de datos (PDF) - Motorola => Freescale
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MC74HC194 Datasheet PDF : 7 Pages
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MC74HC194
PIN DESCRIPTIONS
DATA INPUTS
A, B, C, D (Pins 3, 4, 5, 6)
Parallel data inputs.
SA (Pin 2)
Serial–data input when using shift–right mode.
SD (Pin 7)
Serial–data input when using shift–left mode.
OUTPUTS
QA, QB, QC, QD (Pins 15, 14, 13, 12)
Parallel data outputs.
CONTROL INPUTS
Clock (Pin 11)
Clock Input. The shift register is completely static, allowing
Clock rates down to DC in a continuous or intermittent mode.
Reset (Pin 1)
A low level applied to this pin resets all stages and forces
all outputs low.
S0, S1 (Pins 9, 10)
Mode–select inputs. These inputs control the mode of op-
eration as described in the function table and below.
Parallel Load Mode (S1 = H, S0 = H)
Data is loaded into the device with a positive transition of
the Clock input.
Shift Right Mode (S1 = L, S0 = H)
With a positive transition of the Clock input, each bit is
shifted right (in the direction QA toward QD) one stage and
data on the SA Serial Data Input is shifted into stage A.
Shift Left Mode (S1 = H, S0 = L)
With a positive transition of the Clock input, each bit is
shifted left (in the direction QD toward QA) one stage and
data on the SD Serial Data Input is shifted into stage D.
Hold Mode (S1 = L, S0 = L)
Outputs are held.
SWITCHING WAVEFORMS
tr
tf
CLOCK
90%
50%
VCC
10%
GND
tw
90%
Q 50%
10%
1/fmax
tPLH
tPHL
tTLH
tTHL
tw
VCC
RESET
50%
GND
tPHL
Q
50%
CLOCK
trec
VCC
50%
GND
Figure 1.
Figure 2.
VALID
VCC
DATA OR MODE
50%
GND
tsu
th
VCC
CLOCK
50%
GND
Figure 3.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 4. Test Circuit
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
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