EL4584 Ver la hoja de datos (PDF) - Renesas Electronics

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Lista de partido

EL4584

Horizontal Genlock, 4FSC

Renesas Electronics 

EL4584

Typical Performance Curves (Continued)

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

2.0

1.8

1.6 1.43W

1.4 1.25W

1.2

1.0

PDIP16

JA = +70°C/W

0.8 SO16 (0.150”)

0.6 JA = +80°C/W

0.4

0.2

0

0

25 50 75 100 125 150

AMBIENT TEMPERATURE (°C)

FIGURE 10. PACKAGE POWER DISSIPATION VS AMBIENT TEMPERATURE

Block Diagram

Description Of Operation

The horizontal sync signal (CMOS level, falling leading

edge) is input to HSYNC input (pin 10). This signal is delayed

about 200ns, the falling edge of which becomes the

reference to which the clock output will be locked (see

“Timing Diagrams” on page 5 and page 6). The clock is

generated by the signal on pin 5, OSC IN. There are 2

general types of VCO that can be used with the EL4584; LC

and crystal controlled. Additionally, each type can be either

built-up using discrete components, including a varactor as

the frequency controlling element, or complete, self

contained modules can be purchased with everything inside

a metal can. The modules are very forgiving of PCB layout,

but cost more than discrete solutions. The VCO or VCXO is

used to generate the clock. An LC tank resonator has

greater “pull” than a crystal controlled circuit, but will also be

more likely to drift over time, and thus will generate more

jitter. The “pullability” of the circuit refers to the ability to “pull”

the frequency of oscillation away from its center frequency

by modulating the voltage on the control pin of a VCO

module or varactor, and is a function of the slope and range

FN7174 Rev 3.00

May 9, 2008

of the capacitance-voltage curve of the varactor or VCO

module used. The VCO signal is sent to a divide by N

counter, and to the CLK OUT pin. The divisor N is

determined by the state of pins 1, 2 and 16 and is described

in Table 2. The divided signal is sent, along with the delayed

HSYNC input, to the phase/frequency detector, which

compares the two signals for phase and frequency

differences. Any phase difference is converted to a current at

the charge pump output FILTER (pin 7). A VCO with positive

frequency deviation with control voltage must be used.

Varactors have negative capacitance slope with voltage,

resulting in positive frequency deviation with control voltage

for the oscillators in Figures 12 and 13.

VCO

The VCO should be tuned so its frequency of oscillation is

very close to the required clock output frequency when the

voltage on the varactor is 2.5V. VCXO and VCO modules are

already tuned to the desired frequency, so this step is not

necessary if using one of these units. The range of the

charge pump output (pin 7) is 0V to 5V and it can source or

sink a maximum of about 300µA, so all frequency control

Page 7 of 15

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