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TRC104

2.4 GHz RF Transceiver

Murata Manufacturing 

address detection are disabled. The TRC104 host microcontroller must handle functions such as DC-balanced

data scrambling and CRC generation for Continuous Receive Mode. Note that a valid sender (local device)

address is required for address detection and proper Continuous Receive Mode operation. This address is

configured by writing the address byte(s) into configuration registers 0x0E - 0x12, according to the address length

specified by the ADDR_len bits in configuration register 0x08. The sender address is written least significant byte

first, starting in register 0x0E.

The host microcontroller must be powerful enough to handle the chosen serial data rate (250 kb/s or 1 Mb/s) in

addition to the other functions required for the end application. Data is read from the SDAT pin. To assist in data

recovery, a bit clock is available on the SCLK pin. The state of the SDAT pin is read on the rising edge of SCLK to

recover the demodulated data. Figure 12 and Table 11 show the timing for reading data from SDAT.

C o n tin u o u s M o d e R e c e iv e T im in g

M ODE

SD T

T1

D7

D6

D5

D2

D1

D0

SCL

T2

T3

Figure 12

Item Description

Min Typ Max Unit

T1 MODE to SCLK Time

250

µs

T2 Bit Delay Time

15

ns

T3

SCLK Cycle Time for 1 Mb/s

1

µs

SCLK Cycle Time for 250 kb/s

4

Table 11

5.2 Burst Packet Modes

Burst Packet Mode is enabled when the D_Mode bit of register 0x02 is set to 1. Burst Packet Mode handles

automatic packet features such as preamble generation, address insertion and filtering, DC-balanced data

scrambling/descrambling, and CRC generation and error detection. In Burst Packet Mode the FIFO is enabled

and used for transmitting or receiving packets. In Burst Packet Mode, the host microcontroller does not have the

heavy overhead of bit, byte and packet processing as is the case with the Continuous Mode.

5.2.1 Burst Transmit Mode

Burst Transmit Mode is enabled when the C_Mode bit of configuration register 0x00 is set to 1 and the D_Mode

bit of register 0x02 is set to 1. In Burst Transmit Mode, data is written to the TRC104 before being transmitted,

most significant bit or each byte first. The automatic packet features listed in Section 5.2 are available in Burst

Mode. Once the FIFO is loaded, three additional dummy bits (any value) are clocked in. The MODE pin is then

de-asserted (low) and the packet transmission starts. At the end of the transmission the INT flag is asserted. The

INT flag resets when the TRC104 is placed in another mode. Figure 13 and Table 12 show the serial port timing

parameters for Burst Transmit Mode.

In Burst Mode, the FIFO length is set to match the number of payload data bytes. When transmitting a packet ,

the destination address may obtained from one of two sources, either automatically from configuration registers

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