PEF2015 Ver la hoja de datos (PDF) - Siemens AG
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PEF2015 Datasheet PDF : 84 Pages
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PEF 2015
Overview
Pin Symbol Input (I) Function
No.
Output (O)
9
AD0, D0 I/O
10
AD1, D1
11
AD2, D2
12
AD3, D3
13
AD4, D4
14
AD5, D5
16
AD6, D6
17
AD7, D7
Address/Data Bus; multiplexed bus mode.
Transfers addresses from the µP to the MICO and data
between the µP and the MICO.
Data Bus; demultiplexed bus mode.
Transfers data between the µP and the MICO.
When driving data the pins have push pull
characteristic, otherwise they are in the state high
impedance.
2
A0/ALE I
3
A1
26
A2
27
A3
Address Bus, demultiplexed mode.
Transfers addresses from the µP to the MICO.
Address Latch Enable, multiplexed mode.
ALE controls the on chip address latch in multiplexed
bus mode. While ALE is ’high’ the latch is transparent.
The falling edge latches the current address.
18
RD, DS I
19
WR,
I
R/W
20
CS
I
Note: During reset A0 and A1 are evaluated to
determine the bus mode.
Read, active low, Siemens/Intel bus mode.
When ’low’ a read operation is indicated.
Data Strobe, Motorola bus mode.
A rising edge marks the end of a read or write
operation.
Write, active low, Siemens/Intel bus mode.
When ’low’ a write operation is indicated.
Read/Write, Motorola bus mode.
When ’high’ a valid µP access identifies a read
operation, when ’low’ it identifies a write access.
Chip Select, active ’low’.
A low on this line selects the MICO for a read/write
operation.
Semiconductor Group
10
12.97
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