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PI7C7100CNA

3-Port PCI Bridge

Pericom Semiconductor Corporation 

ADVANCE INFORMATION

PI7C7100

3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566

3. Signal Definitions

3.1 Signal Types

Signal Type Description

PI

PCI Input (3.3V, 5V tolerant)

PIU

PCI Input (3.3V, 5V tolerant) with weak pull-up

PB

PCI 3-state bidirectional (3.3V, 5V tolerant)

PO

PCI Output (3.3V)

PSTS

PTS

PCI Sustained 3-state bidirectional (Active LOW signal which must be driven inactive for one cycle

before being 3-stated to ensure HIGH performance on a shared signal line)

PCI 3-state Output

POD

CI

CIU

PCI Output which either drives LOW (active state) or 3-stated

CMOS Input

CMOS Input with weak pull-up

CID

CMOS Input with weak pull-down

CTO

CMOS 3-state Output

3.2 Signals (Note: Signal name that ends with character ‘#’ is active LOW.)

3.2.1 Primary Bus Interface Signals

Name

Pin #

Type Description

P_AD[31:0]

Y7, W7, Y8, W8, V8, PB

U8, Y9, W9, W10,

V10, Y11, V11, U11,

Y12, W12, V12, V16,

W16, Y16, W17,

Y17, U18, W18, Y18,

U19, W19, Y19, U20,

V20, Y20, T17, R17

Primary Address/Data. Multiplexed address and data bus. Address is

indicated by P_FRAME# assertion. Write data is stable and valid when

P_IRDY# is asserted and read data is stable and valid when P_TRDY# is

asserted. Data is transferred on rising clock edges when both P_IRDY# and

P_TRDY# are asserted. During bus idle, PI7C7100 drives P_AD to a valid

logic level when P_GNT# is asserted.

P_CBE[3:0] V9, U12, U16, V19 PB

Primary Command/Byte Enables. Multiplexed command field and byte

enable field. During address phase, the initiator drives the transaction type

on these pins. After that the initiator drives the byte enables during data

phases. During bus idle, PI7C7100 drives P_CBE[3:0] to a valid logic level

when P_GNT# is asserted.

P_PAR

U15

PB Primary Parity. Parity is even across P_AD[31:0], P_CBE[3:0], and

P_PAR (i.e. an even number of '1's). P_PAR is an input and is valid and

stable one cycle after the address phase (indicated by assertion of

P_FRAME#) for address parity. For write data phases, P_PAR is an input

and is valid one clock after P_IRDY# is asserted. For read data phase,

P_PAR is an output and is valid one clock after P_TRDY# is asserted.

Signal P_PAR is tri-stated one cycle after the PAD lines are 3-stated. During

bus idle, PI7C7100 drives PPAR to a valid logic level when P_GNT# is

asserted.

P_FRAME# W13

PSTS

Primary FRAME (Active LOW). Driven by the initiator of a transaction to

indicate the beginning and duration of an access. The de-assertion of

P_FRAME# indicates the final data phase requested by the initiator. Before

being 3-stated, it is driven to a de-asserted state for one cycle.

4

09/18/00 Rev 1.1

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