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PI7C7100CNA

3-Port PCI Bridge

Pericom Semiconductor Corporation 

ADVANCE INFORMATION

PI7C7100

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3.2.1 Primary Bus Interface Signals (continued)

Name

Pin # Type Description

P_IRDY#

V13 PSTS Primary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to

complete current data phase on the primary side. Once asserted in a data phase, it is not

de-asserted until end of data phase. Before being 3-stated, it is driven to a de-asserted

state for one cycle.

P_TRDY#

U13 PSTS Primary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to

complete current data phase on the primary side. Once asserted in a data phase, it is not

de-asserted until end of data phase. Before being 3-stated, it is driven to a de-asserted

state for one cycle.

P_DEVSEL# Y14

PSTS

Primary Device Select (Active LOW). Asserted by the target indicating that the device

is accepting the transaction. As a master, PI7C7100 waits for the assertion of this signal

within 5 cycles of P_FRAME# assertion; otherwise, terminate with master abort. Before

being 3-stated, it is driven to a de-asserted state for one cycle.

P_STOP#

W14

PSTS Primary STOP (Active LOW). Asserted by the target indicating that the target is

requesting the initiator to stop the current transaction. Before being 3-stated, it is driven

to a de-asserted state for one cycle.

P_LOCK# V14 PSTS Primary LOCK (Active LOW). Asserted by master for multiple transactions to complete.

P_IDSEL

Y10 PI

Primary ID Select. Used as chip select line for Type 0 configuration access to PI7C7100

configuration space.

P_PERR#

Y15 PSTS Primary Parity Error (Active LOW). Asserted when a data parity error is detected for

data received on the primary interface. Before being 3-stated, it is driven to a de-

asserted state for one cycle.

P_SERR#

W15

POD

Primary System Error (Active LOW). Can be driven LOW by any device to indicate a

system error condition, PI7C7100 drives this pin on:

• Address parity error

• Posted write data parity error on target bus

• Secondary S1_SERR# or S2_SERR# asserted

• Master abort during posted write transaction

• Target abort during posted write transaction

• Posted write transaction discarded

• Delayed write request discarded

• Delayed read request discarded

• Delayed transaction master timeout

This signal requires an external pull-up resistor for proper operation.

P_REQ#

W6 PTS Primary Request (Active LOW). This is asserted by PI7C7100 to indicate that it wants

to start a transaction on the primary bus. PI7C7100 de-asserts this pin for at least 2 PCI

clock cycles before asserting it again.

P_GNT#

U7 PI

Primary Grant (Active LOW). When asserted, PI7C7100 can access the primary bus.

During idle and P_GNT# asserted, PI7C7100 will drive P_AD, P_CBE and P_PAR to

valid logic levels.

P_RESET# Y5 PI

Primary RESET (Active LOW). When P_RESET# is active, all PCI signals should be

asynchronously 3-stated.

P_FLUSH# W5 PI

Primary FIFO FLUSH (Active LOW). When P_FLUSH# is active, all primary FIFO(s)

are cleared (invalidate all primary transactions). This signal should be pulled to a static

"high."

P_M66EN V18 –

Reserved for Future Use. Must be tied to ground.

5

09/18/00 Rev 1.1

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