PI7C7100CNA Ver la hoja de datos (PDF) - Pericom Semiconductor Corporation

Número de pieza

componentes Descripción

Lista de partido

PI7C7100CNA

3-Port PCI Bridge

Pericom Semiconductor Corporation 

ADVANCE INFORMATION

PI7C7100

3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566

4.8.4.3

4.9

5.

5.1

5.2

5.2.1

5.2.2

5.3

5.3.1

5.3.2

5.4

5.4.1

5.4.2

6.

6.1

6.2

6.3

6.4

7.

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.3

7.4

8.

8.1

8.2

8.3

9.

9.1

9.2

9.2.1

9.2.2

9.2.3

10.

10.1

10.2

11.

11.1

11.2

11.3

12.

12.1

12.2

13.

Target Abort .......................................................................................................................................................... 27

Concurrent Mode Operation .................................................................................................................................. 27

Address Decoding .................................................................................................................................................. 28

Address Ranges ..................................................................................................................................................... 28

I/O Address Decoding ........................................................................................................................................... 28

I/O Base and Limit Address Registers ................................................................................................................... 28

ISA Mode ............................................................................................................................................................... 29

Memory Address Decoding ................................................................................................................................... 29

Memory-Mapped I/O Base and Limit Address Registers ...................................................................................... 30

Prefetchable Memory Base and Limit Address Registers ...................................................................................... 30

VGA Support .......................................................................................................................................................... 31

VGA Mode ............................................................................................................................................................. 31

VGA Snoop Mode .................................................................................................................................................. 31

Transaction Ordering ........................................................................................................................................... 32

Transactions Governed by Ordering Rules ........................................................................................................... 32

General Ordering Guidelines .................................................................................................................................. 32

Ordering Rules ....................................................................................................................................................... 33

Data Synchronization ............................................................................................................................................. 34

ErrorHandling ...................................................................................................................................................... 35

Address Parity Errors ............................................................................................................................................. 35

Data Parity Errors ................................................................................................................................................... 35

Configuration Write Transactions to Configuration Space ................................................................................... 35

Read Transactions ................................................................................................................................................. 36

Delayed Write Transactions .................................................................................................................................. 36

Posted Write Transactions .................................................................................................................................... 38

Data Parity Error Reporting Summary .................................................................................................................... 39

System Error (SERR#) Reporting ........................................................................................................................... 45

Exclusive Access ................................................................................................................................................... 46

Concurrent Locks ................................................................................................................................................... 46

Acquiring Exclusive Access across PI7C7100 ....................................................................................................... 46

Ending Exclusive Access ....................................................................................................................................... 47

PCI Bus Arbitration .............................................................................................................................................. 48

Primary PCI Bus Arbitration ................................................................................................................................... 48

Secondary PCI Bus Arbitration ............................................................................................................................. 48

Secondary Bus Arbitration Using the Internal Arbiter .......................................................................................... 48

Secondary Bus Arbitration Using an External Arbiter ........................................................................................... 49

Bus Parking ............................................................................................................................................................ 49

Clocks .................................................................................................................................................................... 50

Primary Clock Inputs .............................................................................................................................................. 50

Secondary Clock Outputs ...................................................................................................................................... 50

Reset ...................................................................................................................................................................... 51

Primary Interface Reset .......................................................................................................................................... 51

Secondary Interface Reset ..................................................................................................................................... 51

Chip Reset .............................................................................................................................................................. 51

SupportedCommands ............................................................................................................................................ 52

Primary Interface .................................................................................................................................................... 52

Secondary Interface ............................................................................................................................................... 54

Configuration Registers ....................................................................................................................................... 55

iv

09/18/00 Rev 1.1

Share Link: