PI7C7100CNA Ver la hoja de datos (PDF) - Pericom Semiconductor Corporation

Número de pieza

componentes Descripción

Lista de partido

PI7C7100CNA

3-Port PCI Bridge

Pericom Semiconductor Corporation 

ADVANCE INFORMATION

PI7C7100

3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566

Appendix A - Timing Diagrams

1. Configuration Read Transaction ................................................................................................................................. A-3

2. Configuration Write Transaction ................................................................................................................................A-3

3. Type 1 to Type 0 Configuration Read Transaction (P →S) ......................................................................................A-3

4. Type 1 to Type 0 Configuration Write Transaction (P →S) .....................................................................................A-4

5. Upstream Type 1 to Special Cycle Transaction (S →P) ............................................................................................. A-4

6. Downstream Type 1 to Special Cycle Transaction (P →S) ........................................................................................ A-5

7. Downstream Type 1 to Type 1 Configuration Read Transaction (P →S) ..................................................................A-5

8. Downstream Type 1 to Type 1 Configuration Write Transaction (P →S) .................................................................A-6

9. Upstream Delayed Burst Memory Read Transaction (S →P) ...................................................................................A-6

10. Downstream Delayed Burst Memory Read Transaction (P →S) ..............................................................................A-7

11. Downstream Delayed Memory Read Transaction (P/33MHz →S/33MHz) ............................................................... A-7

12. Downstream Delayed Memory Read Transaction (S2/33MHz →S1/33MHz) ...........................................................A-8

13. Downstream Delayed Memory Read Transaction (S1/33MHz →S2/33MHz) ...........................................................A-8

14. Upstream Delayed Memory Read Transaction (S/33MHz →P/33MHz) ...................................................................A-9

15. Downstream Posted Memory Write Transaction (P/33MHz →S/33MHz) ................................................................ A-9

16. Downstream Posted Memory Write Transaction (S2/33MHz →S1/33MHz) ........................................................... A-10

17. Downstream Posted Memory Write Transaction (S1/33MHz →S2/33MHz) ........................................................... A-10

18. Upstream Posted Memory Write Transaction (S/33MHz →P/33MHz) ................................................................... A-11

19. Downstream Flow-Through Posted Memory Write Transaction (P/33MHz →S/33MHz) ........................................ A-11

20. Downstream Flow-Through Posted Memory Write Transaction (S2/33MHz →S1/33MHz) .................................... A-12

21. Downstream Flow-Through Posted Memory Write Transaction (S1/33MHz →S2/33MHz) .................................... A-12

22. Upstream Flow-Through Posted Memory Write Transaction (S/33MHz →P/33MHz) ............................................ A-13

23. Downstream Delayed I/O Read Transaction (P →S) ............................................................................................... A-13

24. Downstream Delayed I/O Read Transaction (S2/33MHz →S1/33MHz) .................................................................. A-14

25. Downstream Delayed I/O Read Transaction (S1/33MHz →S2/33MHz) .................................................................. A-14

26. Downstream Delayed I/O Read Transaction (S/33MHz →P/33MHz) ...................................................................... A-15

27. Downstream Delayed I/O Write Transaction (P →S) .............................................................................................. A-15

28. Downstream Delayed I/O Write Transaction (S2/33MHz →S1/33MHz) ................................................................. A-16

29. Downstream Delayed I/O Write Transaction (S1/33MHz →S2/33MHz) ................................................................. A-16

30. Upstream Delayed I/O Write Transaction (S →P) ................................................................................................... A-17

Appendix B - Evaluation Board User's Manual

General Information ........................................................................................................................................................... B-3

Frequently Asked Questions ............................................................................................................................................ B-5

Appendix C - Three-Port PCI Bridge Evaluation Board Schematics

PCIChip ............................................................................................................................................................................. C-3

PCI Edge Connector .......................................................................................................................................................... C-4

Secondary 1 PCI Bus ......................................................................................................................................................... C-5

Secondary 2 PCI Bus ......................................................................................................................................................... C-6

Top View ............................................................................................................................................................................ C-7

Appendix D - Representatives and Distributors

viii

09/18/00 Rev 1.1

Share Link: