ML9059E Ver la hoja de datos (PDF) - LAPIS Semiconductor Co., Ltd.

Número de pieza

componentes Descripción

Lista de partido

ML9059E

132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays

LAPIS Semiconductor Co., Ltd. 

LAPIS Semiconductor

FEDL9059E-01

ML9059E

Parameter

Serial clock period

SCL “H” Pulse width

SCL “L” Pulse width

Address setup time

Address hold time

Data setup time

Data hold time

CS setup time

CS hold time

Symbol

tSCYC

tSHW

tSLW

tSAS

tSAH

tSDS

tSDH

tCSS

tCSH

[VDD = 3.7 to 4.5 V, Tj = –40 to +85°C]

Condition

Rated value

Unit

Min Max

250 —

100 —

100 —

150 —

150 — ns

100 —

100 —

150 —

150 —

Note 1: The input signal rise and fall times are specified as 15ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of VDD as the reference.

 Display control output timing

CL(OUT)

FR

VOH

tDFR

VIH

VIL

Parameter

FR Delay time

Symbol

tDFR

Condition

CL = 50 pF

[VDD = 4.5 to 5.5 V, Tj = –40 to +85°C]

Rated value

Unit

Min

Typ

Max

—

10

40

ns

Parameter

FR Delay time

Symbol

tDFR

Condition

CL = 50 pF

[VDD = 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Unit

Min

Typ

Max

—

20

80

ns

Note 1: All timings are specified taking the levels of 20% and 80% of VDD as the reference.

Note 2: Valid only when the device operates in master mode.

13/72

Share Link: