IDT72V3622L10PFG Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT72V3622L10PFG
Integrated Device Technology
IDT72V3622L10PFG Datasheet PDF : 29 Pages
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IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
DESCRIPTION (CONTINUED)
speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which
support clock frequencies up to 100MHz and have read access times as fast
as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on
board each chip buffer data in opposite directions. Communication between
each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox
register has a flag to signal when new mail has been stored.
COMMERCIAL TEMPERATURE RANGE
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
PIN CONFIGURATION
A35 1
A34 2
A33 3
A32 4
VCC 5
A31 6
A30 7
GND 8
A29 9
A28 10
A27 11
A26 12
A25 13
A24 14
A23 15
FWFT 16
A22 17
VCC 18
A21 19
A20 20
A19 21
A18 22
GND 23
A17 24
A16 25
A15 26
A14 27
A13 28
VCC 29
A12 30
TQFP (PNG120, order code: PF)
TOP VIEW
2
90 B35
89 B34
88 B33
87 B32
86 GND
85 B31
84 B30
83 B29
82 B28
81 B27
80 B26
79 VCC
78 B25
77 B24
76 GND
75 B23
74 B22
73 B21
72 B20
71 B19
70 B18
69 GND
68 B17
67 B16
66 VCC
65 B15
64 B14
63 B13
62 B12
61 GND
4660 drw 03
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