LP62S16128B-I Ver la hoja de datos (PDF) - AMIC Technology

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LP62S16128B-I

128K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

Block Diagram

A0

A15

A16

I/O1

I/O8

LP62S16128B-I Series

DECODER

512 X 4096

MEMORY ARRAY

VCC

GND

INPUT

DATA

CIRCUIT

COLUMN I/O

INPUT

DATA

CIRCUIT

I/O9

I/O16

CE

LB

CONTROL

HB

OE

CIRCUIT

WE

Pin Descriptions -- TSOP

Pin No.

Symbol

1 - 5, 18 – 22,

24 – 27, 42 - 44

A0 - A16

6

CE

7 - 10, 13 - 16,

29 - 32, 35 - 38

I/O1 - I/O16

17

WE

39

LB

40

HB

41

OE

11, 33

VCC

12, 34

GND

23, 28

NC

Description

Address Inputs

Chip Enable Input

Data Inputs/Outputs

Write Enable Input

Lower Byte Enable Input (I/O1 to I/O8)

Higher Byte Enable Input (I/O9 to I/O16)

Output Enable Input

Power

Ground

No Connection

(August, 2001, Version 1.0)

2

AMIC Technology, Inc.

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