ISL8500 Ver la hoja de datos (PDF) - Renesas Electronics
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ISL8500 Datasheet PDF : 15 Pages
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ISL8500
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
VOSC
OSC
PWM
COMPARATOR
+-
DRIVER
VIN
LO
PHASE
D
VDDQ
CO
ZFB
VE/A
+-
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C1
C2 R2
ZFB
VOUT
ZIN
C3 R3
COMP
R1
FB
-
+
R4
ISL8500
REFERENCE
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
Feedback Compensation
Figure 21 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The PWM
wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage VOSC.
Modulator Break Frequency Equations
FLC=
---------------------1---------------------
2 x LO x CO
FESR= 2----------x-----E----S--1---R------x-----C-----O---
(EQ. 7)
The compensation network consists of the error amplifier
(internal to the ISL8500) and the impedance networks ZIN and
ZFB. The goal of the compensation network is to provide a
closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin is
the difference between the closed loop phase at f0dB and 180°.
Equation 8 relates the compensation network’s poles, zeros
and gain to the components (R1, R2, R3, C1, C2, and C3) in
FN6611 Rev 0.00
December 10, 2007
Figure 22. Use the following guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
FZ1 = -2---------x-----R--1--2-----x------C----2-
FP1
=
---------------------------1-----------------------------
2
x
R2
x
C-C----11-----+x-----CC----2-2-
FZ2 = 2----------x-------R-----1----+-1----R-----3-------x-----C-----3-
FP2 = -2---------x-----R--1--3-----x------C----3-
(EQ. 8)
Figure 22 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 22. Using the previously mentioned guidelines
should give a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at FP2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 4 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
100
FZ1 FZ2 FP1 FP2
80
60
OPEN LOOP
ERROR AMP GAIN
40
20LOG
20 (R2/R1)
20LOG
0
(VIN/VOSC)
MODULATOR
-20
GAIN
-40
-60
FLC
FESR
10
100
1k
10k 100k
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
Page 13 of 15
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