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ISL8500

2A Standard Buck PWM Regulator

Renesas Electronics 

ISL8500

A more detailed explanation of voltage mode control of a buck

regulator can be found in TB417, entitled “Designing Stable

Compensation Networks for Single Phase Voltage Mode Buck

Regulators.”

Layout Considerations

Layout is very important in high frequency switching converter

design. With power devices switching efficiently between

100kHz and 600kHz, the resulting current transitions from one

device to another cause voltage spikes across the

interconnecting impedances and parasitic circuit elements.

These voltage spikes can degrade efficiency, radiate noise into

the circuit, and lead to device overvoltage stress. Careful

component layout and printed circuit board design minimizes

these voltage spikes.

As an example, consider the turn-off transition of the upper

MOSFET. Prior to turn-off, the MOSFET is carrying the full load

current. During turn-off, current stops flowing in the MOSFET and

is picked up by the Schottky diode. Any parasitic inductance in the

switched current path generates a large voltage spike during the

switching interval. Careful component selection, tight layout of the

critical components, and short, wide traces minimizes the

magnitude of voltage spikes.

There are two sets of critical components in the ISL8500

switching converter. The switching components are the most

critical because they switch large amounts of energy, and

therefore tend to generate large amounts of noise. Next are the

small signal components, which connect to sensitive nodes or

supply critical bypass current and signal coupling.

A multi-layer printed circuit board is recommended. Figure 23

shows the connections of the critical components in the

converter. Note that capacitors CIN and COUT could each

represent numerous physical capacitors. Dedicate one solid

layer, usually a middle layer of the PC board, for a ground plane

and make all critical component ground connections with vias to

this layer. Dedicate another solid layer as a power plane and

break this plane into smaller islands of common voltage levels.

Keep the metal runs from the PHASE terminals to the output

inductor short. The power plane should support the input power

and output power nodes. Use copper filled polygons on the top

and bottom circuit layers for the phase nodes. Use the

remaining printed circuit layers for small signal wiring.

5V

CBP1

VIN

ISL8500

VDD

PHASE

GND

COMP

FB

GND PAD

VIN

CIN

L

VOUT1

D

COUT1

C2

R2

C1

R1

R4

C3 R3

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 23. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

In order to dissipate heat generated by the internal LDO and

MOSFET, the ground pad, pin 13, should be connected to the

internal ground plane through at least four vias. This allows the

heat to move away from the IC and also ties the pad to the

ground plane through a low impedance path.

The switching components should be placed close to the

ISL8500 first. Minimize the length of the connections between

the input capacitors, CIN, and the power switches by placing

them nearby. Position both the ceramic and bulk input

capacitors as close to the upper MOSFET drain as possible.

Position the output inductor and output capacitors between the

upper and Schottky diode and the load.

The critical small signal components include any bypass

capacitors, feedback components, and compensation

components. Place the PWM converter compensation

components close to the FB and COMP pins. The feedback

resistors should be located as close as possible to the FB pin

with vias tied straight to the ground plane as required.

© Copyright Intersil Americas LLC 2007. All Rights Reserved.

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For additional products, see www.intersil.com/en/products.html

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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

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For information regarding Intersil Corporation and its products, see www.intersil.com

FN6611 Rev 0.00

December 10, 2007

Page 14 of 15

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