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AD7265BSU

Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC

Analog Devices 

AD7265

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7265 is a fast, micropower, dual 12-bit, single supply,

A/D converter that operates from a 2.7 V to 5.25 V supply.

When operated from either a 5 V or 3V supply, the AD7265 is

capable of throughput rates of 1 MSPS.

The AD7265 contains two on-chip differential track-and-hold

amplifiers, two successive approximation A/D converters, and a

serial interface with two separate data output pins, and is

housed in a 32-lead LFCSP package, which offers the user

considerable space-saving advantages over alternative solutions.

The serial clock input accesses data from the part but also

provides the clock source for each successive approximation

ADC. The analog input range for the part can be selected to be a

0 V to VREF input or a 2 × VREF input with the analog inputs

configured as either single ended or differential. The AD7265

has an on-chip 2.5 V reference that can be overdriven if an

external reference is preferred.

The AD7265 also features power-down options to allow power

saving between conversions. The power-down feature is

implemented across the standard serial interface, as described in

the Modes of Operation section.

CONVERTER OPERATION

The AD7265 has two successive approximation analog-to-

digital converters, each based around two capacitive DACs.

Figure 3 and Figure 4 show simplified schematics of one of

these ADCs in acquisition and conversion phase, respectively.

The ADC is comprised of control logic, a SAR, and two

capacitive DACs. In Figure 3 (the acquisition phase), SW3, is

closed, SW1 and SW2 are in position A, the comparator is held

in a balanced condition, and the sampling capacitor arrays

acquire the differential signal on the input.

Preliminary Technical Data

VIN+

VIN–

B

CS

A SW1

A SW2 CS

B

VREF

CAPACITIVE

DAC

COMPARATOR

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 3. ADC Acquisition Phase

When the ADC starts a conversion (Figure 4), SW3 opens and

SW1 and SW2 move to position B, causing the comparator to

become unbalanced. Both inputs are disconnected once the

conversion begins. The control logic and the charge redistribu-

tion DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is

rebalanced, the conversion is complete. The control logic

generates the ADC output code. The output impedances of the

sources driving the VIN+ and VIN– pins must be matched;

otherwise, the two inputs will have different settling times,

resulting in errors.

VIN+

VIN–

B

CS

A SW1

A SW2 CS

B

VREF

CAPACITIVE

DAC

COMPARATOR

SW3

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 4. ADC Conversion Phase

Rev. PrA | Page 10 of 16

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