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AD7265BSU

Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC

Analog Devices 

AD7265

Preliminary Technical Data

Parameter

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL

Floating State Leakage Current

Floating State Output Capacitance3

Output Coding

CONVERSION RATE

Conversion Time

Track/Hold Acquisition Time3

Throughput Rate

POWER REQUIREMENTS

VDD

VDRIVE

IDD6

Normal Mode (Static)

Operational, fs = 1 MSPS

Partial Power-Down Mode

Partial Power-Down Mode

Full Power-Down Mode

Power Dissipation6

Normal Mode (Operational)

Partial Power-Down (Static)

Full Power-Down (Static)

Specification Unit

Test Conditions/Comments

VDRIVE – 0.2

0.4

V min

V max

±1

µA max

10

pF max

Straight (Natural) Binary

Twos Complement

SGL/DIFF = 1 with 0 V to VREF range selected

SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × VREF range

14

SCLK Cycles TBD ns with SCLK = 16 MHz

100

ns max

TBD

MSPS max

2.7/5.25

2.7/5.25

TBD

3.3

2.3

TBD

TBD

TBD

V min/V max

V min/V max

mA max

mA max

mA max

mA max

µA max

µA max

Digital I/Ps = 0 V or VDRIVE

VDD = 5 V

VDD = 3 V

fs = 200 kSPS

Static

16.5

mW max

VDD = 5 V

TBD

mW max

TBD

mW max

NOTES

1 Temperature ranges as follows: -40°C to +125°C

2 See Terminology section.

3 Sample tested during initial release to ensure compliance.

4 Relates to Pins DCAPA or DCAPB.

5 See Reference section for DCAPA, DCAPB output impedances.

6 See Power Versus Throughput Rate section.

TIMING SPECIFICATIONS

Table 2. AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, TA = TMAX to TMIN, unless otherwise noted

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK

10

kHz min

20

MHz max

tCONVERT

14 × tSCLK

ns max

tSCLK = 1/fSCLK

700

ns max

fSCLK = 20 MHz,

tQUIET

35

ns max

Minimum time between end of serial read and next falling edge of CS

t2

10

ns min

CS to SCLK setup time

t3

TBD

ns max

Delay from CS until DOUTA and DOUTB are three-state disabled

t4

TBD

ns max

Data access time after SCLK falling edge.

t5

0.4tSCLK

ns min

SCLK low pulse width

t6

0.4tSCLK

ns min

SCLK high pulse width

t7

TBD

ns min

SCLK to data valid hold time

t8

25

ns max

CS rising edge to DOUTA, DOUTB, high impedance

t9

TBD

ns min

SCLK falling edge to DOUTA, DOUTB, high impedance

TBD

ns max

SCLK falling edge to DOUTA, DOUTB, high impedance

Rev. PrA | Page 4 of 16

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