DS2141A Ver la hoja de datos (PDF) - Maxim Integrated

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DS2141A

T1 Controller

Maxim Integrated 

DS2141A

CCR1: COMMON CONTROL REGISTER 1 (37h)

(MSB)

(LSB)

TESE

P34F

RSAO

-

SCLKM RESE

PLB

LLB

SYMBOL POSITION NAME AND DESCRIPTION

TESE

CCR1.7

Transmit Elastic Store Enable.

0=elastic store is bypassed.

1=elastic store is enabled.

P34F

CCR1.6

Function of Pin 34.

0=Receive Loss of Sync (RLOS).

1=Loss of Transmit Clock (LOTC).

RSAO

CCR1.5

Receive Signaling All 1's.

0=allow robbed signaling bits to appear at RSER.

1=force all robbed signaling bits at RSER to 1.

-

CCR1.4 Not Assigned. Should be set to 0 when written to.

SCLKM

CCR1.3

SYSCLK Mode Select.

0=if SYSCLK is 1.544 MHz.

1=if SYSCLK is 2.048 MHz.

RESE

CCR1.2

Receive Elastic Store Enable.

0=elastic store is bypassed.

1=elastic store is enabled.

PLB

CCR1.1 Payload Loopback.

0=loopback disabled.

1=loopback enabled.

LLB

CCR1.0 Local Loopback.

0=loopback disabled.

1=loopback enabled.

PAYLOAD LOOPBACK

When CCR1.1 is set to a 1, the DS2141A will be forced into Payload LoopBack (PLB). Normally, this

loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS2141A will

loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit

section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are

reinserted by the DS2141A. When PLB is enabled, the following will occur:

1. Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK.

2. All of the receive side signals will continue to operate normally.

3. The TCHCLK and TCHBLK signals are forced low.

4. Data at the TSER pin is ignored.

5. The TLCLK signal will become synchronous with RCLK instead of TCLK.

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