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DS2141A

T1 Controller

Maxim Integrated 

DS2141A

4.0 STATUS AND INFORMATION REGISTERS

There is a set of three registers that contain information on the current real time status of the DS2141A:

Status Register 1 (SR1), Status Register 2 (SR2), and the Receive Information Register (RIR). When a

particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be

set to a 1. All of the bits in these registers operate in a latched fashion. This means that if an event occurs

and a bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. The bit will be

cleared when it is read and it will not be set again until the event has occurred again (or in the case of

RLOS, if loss of sync is still present).

The user will always precede a read of these registers with a write. The byte written to the register will

inform the DS2141A which bits the user wishes to read and have cleared. The user will write a byte to

one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit

positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location,

the read register will be updated with current value and it will be cleared. When a 0 is written to a bit

position, the read register will not be updated and the previous value will be held. A write to the status

and information registers will be immediately followed by a read of the same register. The read result

should be logically AND’ed with the mask byte that was just written and this value should be written

back into the same register to insure that the bit does indeed clear. This second write is necessary because

the alarms and events in the status registers occur asynchronously in respect to their access via the

parallel port. This scheme allows an external microcontroller or microprocessor to individually poll

certain bits without disturbing the other bits in the register. This operation is key in controlling the

DS2141A with higher-order software languages.

The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2

pins respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked

from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2)

respectively.

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