DS2141A Ver la hoja de datos (PDF) - Maxim Integrated
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DS2141A Datasheet PDF : 39 Pages
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DS2141A
ADDRESS
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
R/W
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REGISTER NAME
Receive Signaling
Register 6
Receive Signaling
Register 7
Receive Signaling
Register 8
Receive Signaling
Register 9
Receive Signaling
Register 10
Receive Signaling
Register 11
Receive Signaling
Register 12
Receive Channel
Blocking Register 1
Receive Channel
Blocking Register 2
Receive Channel
Blocking Register 3
Interrupt Mask Register 2
Transmit Signaling
Register 1
Transmit Signaling
Register 2
Transmit Signaling
Register 3
ADDRESS R/W REGISTER NAME
73
R/W Transmit Signaling
Register 4
74
R/W Transmit Signaling
Register 5
75
R/W Transmit Signaling
Register 6
76
R/W Transmit Signaling
Register 7
77
R/W Transmit Signaling
Register 8
78
R/W Transmit Signaling
Register 9
79
R/W Transmit Signaling
Register 10
7A
R/W Transmit Signaling
Register 11
7B
R/W Transmit Signaling
Register 12
7C
R/W LI Control Register Byte
1
7D
R/W LI Control Register Byte
2
7E
R/W Transmit FDL Register
7F
R/W Interrupt Mask Register 1
Note: All values indicated within the Address
column are hexadecimal.
2.0 PARALLEL PORT
The DS2141A is controlled via a multiplexed bidirectional address/data bus by an external
microcontroller or microprocessor. The DS2141A can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in the AC
Electrical Characteristics for more details. The multiplexed bus on the DS2141A saves pins because the
address information and data information share the same signal paths. The addresses are presented to the
pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of
the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2141A
latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during
the later portion of the DS or WR pulses. In a read cycle, the DS2141A outputs a byte of data during the
latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high
impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing.
3.0 CONTROL REGISTERS
The operation of the DS2141A is configured via a set of six registers. Typically, the control registers are
only accessed when the system is first powered up. Once, the DS2141A has been initialized, the control
registers will only need to be accessed when there is a change in the system configuration. There are two
Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and
two Common Control Registers (CCR1 and CCR2). Each of the six registers is described below.
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