QL7160-4PT208C Ver la hoja de datos (PDF) - QuickLogic Corporation

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Lista de partido

QL7160-4PT208C

Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

4/ (FOLSVH3OXV 'DWD 6KHHW 5HY $

Quad net

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&ORFN 6RXUFH

Logic Cells (Internal)

Clock Pad

7DEOH  (FOLSVH3OXV &ORFN 'HOD\

3DUDPHWHUV

&ORFN 3HUIRUPDQFH

*OREDO

'HGLFDWHG

Clock signal generated internally 1.51 ns (max)

Clock signal generated externally 2.06 ns (max)

1.73 ns (max)

&ORFN 6HJPHQW

tPGCKa

tBGCK

7DEOH  (FOLSVH3OXV *OREDO &ORFN 'HOD\

3DUDPHWHU

0LQ

Global clock pin delay to quad net

-

Global clock tree delay (quad net to

flip-flop)

-

9DOXH

0D[

1.34 ns

0.56 ns

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/RFNHG /RRS

Programmable Clock

External Clock

Global Clock Buffer

Global Clock

tPGCK

Clock

Select

tBGCK

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