LTC6905C(RevA) Ver la hoja de datos (PDF) - Linear Technology
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LTC6905C Datasheet PDF : 8 Pages
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BLOCK DIAGRA
V+
1
RSET
IRES
SET
3
–
+– VBIAS
+
2 GND
LTC6905
VR(EVS+
=
–
1V ±5%
VSET)
+
GAIN = 1
–
MASTER OSCILLATOR
IRES
PROGRAMMABLE
DIVIDER
(÷1, 2 OR 4)
fOSC
=
fMO
N
OUT
5
DIVIDER
SELECT
THREE-STATE
INPUT DETECT
V+
15µA
DIV
4
15µA
GND
6905 BD
U
THEORY OF OPERATIO
As shown in the Block Diagram, the LTC6905’s master
oscillator is controlled by the ratio of the voltage between
the V+ and SET pins and the current entering the SET pin
(IRES). The voltage on the SET pin is forced to approxi-
mately 1V below V+ by the PMOS transistor and its gate
bias voltage.
A resistor RSET, connected between the V+ and SET pins,
“locks together” the voltage (V+ – VSET) and current, IRES,
variation. This provides the LTC6905’s high precision. The
master oscillation frequency reduces to:
f
MO
=
168.5MHz •10kΩ
RSET
+
1.5MHz
To extend the output frequency range, the master oscilla-
tor signal is divided by 1, 2 or 4 before driving OUT (Pin
5). The LTC6905 is optimized for use with resistors
between 10k and 25k, corresponding to oscillator fre-
quencies between 17.225MHz and 170MHz. The divide-
by value is determined by the state of the DIV input
(Pin 4). Tie DIV to V+ or drive it to within 0.4V of V+ to
select ÷1. This is the highest frequency range, with the
master output frequency passed directly to OUT. The DIV
pin may be floated or driven to midsupply to select ÷2, the
intermediate frequency range. The lowest frequency range,
÷4, is selected by tying DIV to GND or driving it below
0.5V. Figure 1 shows the relationship between RSET,
divider setting and output frequency, including the over-
lapping frequencies.
30
25
÷4 ÷2
÷1
20
15
10
5
10
60
110
160
OUTPUT FREQUENCY (MHz)
6905 F01
Figure 1. RSET vs Output Frequency
6905fa
5
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