LTC6905C(RevA) Ver la hoja de datos (PDF) - Linear Technology
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LTC6905C Datasheet PDF : 8 Pages
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LTC6905
APPLICATIO S I FOR ATIO
SELECTING THE DIVIDER SETTING AND RESISTOR
The LTC6905’s master oscillator has a frequency range
spanning 68.9MHz to 170MHz. A programmable divider
extends the frequency range from 17.225MHz to 170MHz.
Table 1 describes the recommended frequencies for each
divider setting. Note that the ranges overlap; at some
frequencies there are two divider/resistor combinations
that result in the same frequency. Choosing a higher
divider setting will result in less jitter at the expense of
slightly higher supply current.
Table 1. Frequency Range vs Divider Setting
DIVIDER SETTING
÷1 ⇒ DIV (Pin 4) = V+
÷2 ⇒ DIV (Pin 4) = Floating
÷4 ⇒ DIV (Pin 4) = GND
FREQUENCY RANGE
68.9MHz to 170MHz
34.45MHz to 85MHz
17.225MHz to 43MHz
After choosing the proper divider setting, determine the
correct frequency-setting resistor. Because of the linear
correspondence between oscillation period and resis-
tance, a simple equation relates resistance with frequency.
RSET
=
10k
N
•
⎛
⎝⎜
168.5MHz
fOSC – 1.5MHz
⎞
⎠⎟
,
N
=
⎧⎨⎪12
⎩⎪4
(RSETMIN = 10k, RSETMAX = 25k)
Any resistor, RSET, tolerance adds to the inaccuracy of the
oscillator, fOSC.
START-UP TIME
The start-up time and settling time to within 1% of the final
frequency is typically 100µs.
MAXIMUM OUTPUT LOAD
The LTC6905 output (Pin 5) can drive a capacitive load
(CLOAD) of 5pF or more. Driving a CLOAD greater than 5pF
depends on the oscillator’s frequency (fOSC) and output
resistance (ROUT). The output rise time or fall time due to
ROUT and CLOAD is equal to 2.2 • ROUT • CLOAD (from 10%
to 90% of the rise or fall transition). If the total output rise
time plus fall time is arbitrarily specified to be equal to or
less than 20% of the oscillator’s period (1/fOSC), then the
maximum output CLOAD in picofarads (pF) should be equal
to or less than [45454/(ROUT • fOSC)] (ROUT in ohms and
fOSC in MHz).
6
Example: An LTC6905 is operating with a 3V power supply
and is set for a fOSC = 50MHz.
ROUT with V+ = 3V is 27Ω (using the ROUT vs V+ graph in
the Typical Performance Characteristics).
The maximum output CLOAD should be equal to or less
than [45454/(27 • 50)] = 33.6pF.
The lowest resistive load Pin 5 can drive can be calculated
using the minimum high level output voltage in the Elec-
trical Characteristics. With a V+ equal to 5.5V and 4mA
output current, the minimum high level output voltage is
5V and the lowest resistive load Pin 5 can drive is 1.25k
(5V/4mA). With a V+ equal to 2.7V and 4mA output
current, the minimum high level output voltage is 1.9V and
the lowest resistive load Pin 5 can drive is 475Ω (1.9V/4mA).
FREQUENCY ACCURACY AND POWER SUPPLY NOISE
The frequency accuracy of the LTC6905 may be affected
when its power supply generates noise with frequency
contents equal to fMO/64 or its multiples (fMO is the internal
LTC6905 master oscillator frequency before the divider
and fMO/64 is the master oscillator control loop fre-
quency). If for example, the master oscillator frequency is
set equal to 80MHz and the LTC6905 is powered by a
switching regulator, then the oscillator frequency may
show an additional error if the switching frequency is
1.4MHz (80MHz/64).
JITTER AND POWER SUPPLY NOISE
If the LTC6905 is powered by a supply that has frequency
contents equal to the output frequency then the oscillators
jitter may increase. In addition, power supply ripple in
excess of 20mV at any frequency may increase jitter.
JITTER AND DIVIDE RATIO
At a given output frequency, a higher master oscillator
frequency and a higher divide ratio will result in lower jitter
and higher power supply dissipation. Indeterminate jitter
percentage will decrease by a factor of slightly less than
the square root of the divider ratio, while determinate jitter
will not be similarly attenuated. Please consult the speci-
fication tables and Jitter vs Frequency graph showing jitter
at various divider ratios.
6905fa
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