BR25G128FVM-3GTR Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR25G128FVM-3GTR Datasheet PDF : 36 Pages
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BR25G128-3
Datasheet
3. Write Command (WRITE)
CSB
SCK
SI
～～
0 1 2 3 4 5 6 7 8 9 10 11 ～ ～
00 0 0 0 0
10
～～
*
* A13 A12 ～ ～
23 24
A1 A0 D7 D6
～～
～～
30 31
～～
～ ～ D2 D1 D 0
SO High-Z
～～
Figure 40. Write command
＊ =Don't Care
By write command, data of EEPROM can be written. As for this command, set CSB LOW, then input address and data
after write ope code. Then, by making CSB HIGH, the EEPROM starts writing. The write time of EEPROM requires time
of tE/W (Max 5ms). During tE/W, other than read status register command is not accepted. Set CSB HIGH between taking
the last data (D0) and rising the next SCK clock. At the other timing, write command is not executed, and this write
command is cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input
without setting CSB HIGH, 2byte or more data can be written for one tE/W. Up to 64 arbitrary bytes can be written. In page
write, the insignificant 6 bit of the designated address is incremented internally at every time when data of 1 byte is input
and data is written to respective addresses. When data of the maximum bytes or higher is input, address rolls over, and
previously input data is overwritten.
4. Write Status Register, Read Status Register Command (WRSR/RDSR)
CSB
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
00 0 00 0
bit7
bit6
bit5 bit4 bit3
bit2
bit1
bit0
0
1 WPEN *
*
* BP1 BP0 *
*
SO High-Z
*=Don't care
Figure 41. Write status register
Write status register command can write data of status register. The data can be written by this command are 3 bits, that
is, WPEN (bit7), BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of
EEPROM can be set. As for this command, set CSB LOW, and input ope code of write status register, and input data.
Then, by making CSB HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CSB rise,
set CSB HIGH between taking the last data bit (bit0) and the next SCK clock rising. At the other timing, command is
cancelled. Write disable block is determined by BP1 BP0, and the block can be selected from 1/4, 1/2, and entire of
memory array (Refer to the write disable block setting table.). To the write disabled block, write cannot be made, and only
read can be made.
CSB
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SI
00
0
0
High-Z
SO
0
1
0
1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
WPEN 0 0 0 BP1 BP0 WEN R/B
Figure 42. Read status register command
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TSZ02201-0R2R0G100670-1-2
19.Mar.2014 Rev.001
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