Features
• Distributes one differential LVPECL reference clock to six differential HCSL clock pairs and two singleended LVTTL MREF clocks
• HCSL current levels controlled by IREF current reference and MULT_0:1 current multiplier pins
• Host clock frequency division selected via the SEL_A, SEL_B, and SEL_U input signals
• Active-low PWR_DWN# signal disables all outputs
• Tristate output control via SEL_T facilitates board testing
• Available in a 48-pin SSOP and TSSOP