Description
The Intersil ACS280MS is a Radiation Hardened 9-bit odd/even parity generator checker device. Both odd and even parity outputs are available for generating or checking parity for words up to 9 bits long. Even parity is indicated (EVEN output high) when an even number of data inputs are high. Odd parity is indicated (ODD output high) when an odd number of data inputs are high. Parity checking for larger words can be accomplished by tying EVEN output to any input of an additional ACS280MS.

FEATUREs
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96708 and Intersil’ QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
    - VIL = 30% of VCC Max
    - VIH = 70% of VCC Min
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 23ns (Max), 15ns (Typ)