GENERAL DESCRIPTION
The AD9549 provides synchronization for many systems including synchronous optical networks (SONET/SDH). The AD9549 generates an output clock, synchronized to one of two external input references. The external references may contain significant time jitter, also specified as phase noise. Using a digitally controlled loop and holdover circuitry, the AD9549 continues to generate a clean (low jitter), valid output clock during a ‘loss of reference’ condition, even when both references have failed.
The AD9549 operates over an industrial temperature range, spanning -40°C to +85°C.

FEATURES
   Flexible Reference Inputs
   Input frequencies 8 kHz to 750 MHz
   Two reference inputs
   Loss of Reference indicators
   Auto and Manual Holdover modes
   Auto and Manual Switchover modes
   Smooth A to B phase transition on outputs
   Excellent stability in holdover mode
   Programmable 16+1-bit Input Divider, R
   Differential HSTL Clock Output
   Output frequencies to 750 MHz
   Low Jitter clock doubler for frequencies > 400 MHz
   Single-ended CMOS output; frequencies < 50MHz
   Programmable Digital Loop Filter (< 1 Hz to ~100 kHz)
   High Speed Digitally Controlled Oscillator (DCO) core
      DDS with integrated 14 bit DAC
   Excellent Dynamic Performance
   Programmable 16+1-bit Feedback Divider, S
   Software controlled power-down
   64-lead LFCSP package

APPLICATIONS
   Network Synchronization
   Reference Clock Jitter Cleanup
   SONET/SDH Clocks up to OC-192, Including FEC
   Stratum 3/3E Reference Clocks
   Wireless Base Stations, Controllers
   Cable Infrastructure
   Data Communications