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ADSP-TS101SAB1-100 Hoja de datos - Analog Devices

ADSP-TS101S image

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ADSP-TS101SAB1-100

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48 Pages

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ADI
Analog Devices ADI

GENERAL DESCRIPTION
The ADSP-TS101S TigerSHARC® processor is an ultrahigh performance, Static SuperscalarTM †processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new standard of performance for digital signal processors. The TigerSHARC processor’s Static Superscalar architecture lets the processor execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.


FEATURES
   300 MHz, 3.3 ns instruction cycle rate
   6M bits of internal—on-chip—SRAM memory
   19 mm × 19 mm (484-ball) or 27 mm × 27 mm
      (625-ball) PBGA package
   Dual computation blocks—each containing an ALU, a
      multiplier, a shifter, and a register file
   Dual integer ALUs, providing data addressing and pointer
      manipulation
   Integrated I/O includes 14-channel DMA controller, external
      port, 4 link ports, SDRAM controller, programmable flag
      pins, 2 timers, and timer expired pin for system integration
   1149.1 IEEE compliant JTAG test access port for on-chip
      emulation
   On-chip arbitration for glueless multiprocessing with up to
      8 TigerSHARC processors on a bus


BenefitS
   Provides high performance Static Superscalar DSP
      operations, optimized for telecommunications infrastructure
      and other large, demanding multiprocessor DSP
      applications
   Performs exceptionally well on DSP algorithm and I/O
      benchmarks (see benchmarks in Table 1 and Table 2)
   Supports low overhead DMA transfers between internal
      memory, external memory, memory-mapped peripherals,
      link ports, other DSPs (multiprocessor), and host
      processors
   Eases DSP programming through extremely flexible
      instruction set and high-level language-friendly DSP architecture
   Enables scalable multiprocessing systems with low
      communications overhead

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