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AM29BDS323DT11AWKI(2001) Hoja de datos - Advanced Micro Devices

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AM29BDS323DT11AWKI

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AMD
Advanced Micro Devices AMD

GENERAL DESCRIPTION
The Am29BDS323 is a 32 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 2,097,152 words of 16 bits each. This device uses a single VCC of 1.7 to 1.9 V to read, program, and erase the memory array. A 12.0-volt VPP may be used for faster program performance if desired. The device can also be programmed in standard EPROM programmers.

DISTINCTIVE CHARACTERISTICS
■ Single 1.8 volt read, program and erase (1.7 to 1.9 volt)
■ Multiplexed Data and Address for reduced I/O count
   — A0–A15 multiplexed as D0–D15
   — Addresses are latched with AVD# control inputs
      while CE# low
■ Simultaneous Read/Write operation
   — Data can be continuously read from one bank
      while executing erase/program functions in other
      bank
   — Zero latency between read and write operations
■ Read access times at 40 MHz
   — Burst access times of 20 ns @ 30 pF
      at industrial temperature range
   — Asynchronous random access times
      of 110 ns @ 30 pF
   — Synchronous random access times
      of 120 ns @ 30 pF
■ Burst length
   — Continuous linear burst
■ Power dissipation (typical values, 8 bits switching, CL = 30 pF)
   — Burst Mode Read: 25 mA
   — Simultaneous Operation: 40 mA
   — Program/Erase: 15 mA
   — Standby mode: 0.2 µA
■ Sector Architecture
   — Eight 4 Kword sectors and sixty-three sectors of
      32 Kwords each
   — Bank A contains the eight 4 Kword sectors and
      fifteen 32 Kword sectors
   — Bank B contains forty-eight 32 Kword sectors
■ Sector Protection
   — Software command sector locking
   — WP# protects the last two boot sectors
   — All sectors locked when VPP = VIL
■ Software command set compatible with JEDEC 42.4 standards
   — Backwards compatible with Am29F and Am29LV
      families
■ Minimum 1 million erase cycle guarantee per sector
■ 20-year data retention at 125°C
   — Reliable operation for the life of the system
■ Embedded Algorithms
   — Embedded Erase algorithm automatically
      preprograms and erases the entire chip or any
      combination of designated sectors
   — Embedded Program algorithm automatically
      writes and verifies data at specified addresses
■ Data# Polling and toggle bits
   — Provides a software method of detecting
      program and erase operation completion
■ Erase Suspend/Resume
   — Suspends an erase operation to read data from,
      or program data to, a sector that is not being
      erased, then resumes the erase operation
■ Hardware reset input (RESET#)
   — Hardware method to reset the device for reading
      array data
■ CMOS compatible inputs, CMOS compatible outputs
■ Low VCC write inhibit
■ Package Option
   — 47-ball FBGA

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