Functional Description
The CY7B9945V high-speed multi-phase PLL clock buffer offers user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems.

FEATUREs
• 500 ps max. Total Timing Budget™ (TTB™) window
• 24–200 MHz input/output operation
• Low output-output skew < 200 ps
• 10 + 1 LVTTL outputs driving 50Ω terminated lines
• Dedicated feedback output
• Phase adjustments in 625/1300 ps steps up to +10.4 ns
• 3.3V LVTTL/LVPECL, fault-tolerant, and hot-insertable reference inputs
• Multiply/divide ratios of 1–6, 8, 10, and 12
• Individual output bank disable
• Output high-impedance option for testing purposes
• Integrated phase-locked loop (PLL) with lock indicator
• Low cycle-cycle jitter (<100 ps peak-peak)
• 3.3V operation
• Industrial temperature range: –40°C to +85°C
• 52-pin 1.4-mm TQFP package