Functional Description
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1 Mbit x 36 / 2 Mbit x 18 / 512K x72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460AV33/ CY7C1462AV33/CY7C1464AV33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions.The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin compatible and functionally equivalent to ZBT devices.

FEATUREs
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
   — Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
   — 2.6 ns (for 250-MHz device)
   — 3.2 ns (for 200-MHz device)
   — 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV33 and CY7C1462AV33 are available in
   lead-free 100-pin TQFP and 165-Ball fBGA packages;
   CY7C1464AV33 available in 209-Ball fBGA package
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option