Functional Description
The CY7C1648KV18, and CY7C1650KV18 are 1.8-V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry.

FEATUREs
■ 144-Mbit density (8 M × 18, 4 M × 36)
■ 450-MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
■ Available in 2.0-clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
    ❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.0-cycle read latency when DOFF is asserted high
■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted low
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]
    ❐ Supports both 1.5 V and 1.8 V I/O supply
■ High-speed transceiver logic (HSTL) inputs and variable drive HSTL output buffers
■ Available in 165-ball fine-pitch ball grid array (FBGA) package (15 × 17 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement