datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga
HOME  >>>  Digital Core Design  >>> D16550 PDF

D16550 Hoja de datos - Digital Core Design

D16550 image

Número de pieza
D16550

componentes Descripción

Other PDF
  no available.

PDF
DOWNLOAD     

page
7 Pages

File Size
156.2 kB

Fabricante
DCD
Digital Core Design DCD

OVERVIEW
The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-toparallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU.


KEY FEATURES
● Software compatible with 16450 and 16550 UARTs
● Configuration capability
● Separate configurable BAUD clock line
● Two modes of operation: UART mode and FIFO mode
● Majority Voting Logic
● In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU
● Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
● In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
● Independently controlled transmit, receive, line status, and data set interrupts
● False start bit detection
● 16 bit programmable baud generator
● MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
    ○ Fully programmable serial-interface characteristics:
    ○ 5-, 6-, 7-, or 8-bit characters
    ○ Even, odd, or no-parity bit generation and
    ○ 1-, 1½-, or 2-stop bit generation detection
    ○ Baud generation
● Complete status reporting capabilities
● Line break generation and detection. Internal diagnostic capabilities:
    ○ Loop-back controls for communications link fault isolation
    ○ Break, parity, overrun, framing error simulation
● Two DMA Modes allows single and multitransfer
● Technology independent HDL Source Code
● Full prioritized interrupt system controls
● Fully synthesizable static design with no internal tri-state buffers


APPLICATIONS
● Serial Data communications applications
● Modem interface

Page Link's: 1  2  3  4  5  6  7 

Número de pieza
componentes Descripción
PDF
Fabricante
Configurable UART with FIFO
Ver
Unspecified
FIFO UART
Ver
A1 PROs co., Ltd.
FIFO UART
Ver
IMP, Inc
Quard Uart with 256-Byte FIFO
Ver
IK Semicon Co., Ltd
QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO ( Rev : 1994 )
Ver
Exar Corporation
QUAD UART WITH 16-BYTE FIFO’S ( Rev : 1994 )
Ver
Exar Corporation
2.97V TO 5.5V UART WITH 16-BYTE FIFO ( Rev : 2005 )
Ver
Exar Corporation
2.97V TO 5.5V UART WITH 16-BYTE FIFO
Ver
Exar Corporation
2.90V TO 5.5V UART WITH 32-BYTE FIFO
Ver
Exar Corporation
Dual USB UART / FIFO I.C. ( Rev : 2004 )
Ver
Future Technology

Share Link: GO URL

EnglishEnglish Korean한국어 Chinese简体中文 Japanese日本語 Russianрусский

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]