General Description
These positive-edge triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input.
Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

FEATUREs
■ Contains six flip-flops with single-rail outputs
■ Buffered clock and direct clear inputs
■ Individual data input to each flip-flop
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per flip-flop 38 mW