General Description
This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit.

FEATUREs
■ Complementary outputs
■ Direct overriding (data) inputs
■ Gated clock inputs
■ Parallel-to-serial data conversion
■ Typical frequency 35 MHz
■ Typical power dissipation 105 mW