The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an  efficient 24-bit DSP core, program and data memories, various peripherals, and support  circuitry.

FEATURES
Digital Signal Processing Core
• Efficient 24-bit DSP56000 core
• Up to 40 Million Instructions Per Second (MIPS), 25 ns instruction cycle at  80 MHz; up to 33 MIPS, 30.3 ns instruction cycle at 66 MHz
• Up to 240 Million Operations Per Second (MOPS) at 80 MHz; up to 198 MOPS  at 66 MHz
• Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks
• Highly parallel instruction set with unique DSP addressing modes
• Two 56-bit accumulators including extension bits
• Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
• Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles
• 56-bit addition/subtraction in 1 instruction cycle
• Fractional and integer arithmetic with support for multiprecision arithmetic
• Hardware support for block-floating point FFT
• Hardware nested DO loops
• Zero-overhead fast interrupts (2 instruction cycles)
• Four 24-bit internal data buses and three 16-bit internal address buses for  maximum information transfer on-chip

Memory
• On-chip Harvard architecture permitting simultaneous accesses to program  and two data memories
• 512 × 24-bit on-chip Program RAM and 64 × 24-bit bootstrap ROM
• Two 256 × 24-bit on-chip data RAMs
• Two 256 × 24-bit on-chip data ROMs containing sine, A-law, and µ-law tables
• External memory expansion with 16-bit address and 24-bit data buses
• Bootstrap loading from external data bus, Host Interface, or Serial  Communications Interface

Peripheral and Support Circuits
• Byte-wide host interface (HI) with Direct Memory Access (DMA) support (or  fifteen Port B GPIO lines)
• SSI support:
    – Supports serial devices with one or more industry-standard codecs, other  DSPs, microprocessors, and Motorola-SPI-compliant peripherals
    – Asynchronous or synchronous transmit and receive sections with separate  or shared internal/external clocks and frame syncs
    – Network mode using frame sync and up to 32 software-selectable time  slots
    – 8-bit, 12-bit, 16-bit, and 24-bit data word lengths
• SCI for full duplex asynchronous communications (or three additional Port C  GPIO lines)
• One 24-bit timer/event counter (or one additional GPIO line)
• Double-buffered peripherals
• Up to twenty-five General Purpose Input/Output (GPIO) pins
• One non-maskable and two maskable external interrupt/mode control pins
• On-Chip Emulation (OnCE) port for unobtrusive, processor speedindependent debugging
• Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer  for the DSP core clock with a wide input frequency range (12.2 KHz to 80  MHz)

Miscellaneous Features
• Power-saving Wait and Stop modes
• Fully static, HCMOS design for specified operating frequency down to dc
• Three packages available:
    – 132-pin Plastic Quad Flat Pack (PQFP); 1.1 × 1.1 × 0.19 inches
    – 144-pin Thin Quad Flat Pack (TQFP); 20 × 20 × 1.5 mm
    – 132-pin Ceramic Pin Grid Array (PGA); 1.36 × 1.35 × 0.125 inches