DEVICE OVERVIEW
This document contains device family specific information for the dsPIC30F family of Digital Signal Controller (DSC) devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high performance 16-bit microcontroller (MCU) architecture.

High Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• 84 base instructions
• 24-bit wide instructions, 16-bit wide data path
• Linear program memory addressing up to 4M
   instruction words
• Linear data memory addressing up to 64 Kbytes
• Up to 144 Kbytes on-chip Flash program space
• Up to 48K instruction words
• Up to 8 Kbytes of on-chip data RAM
• Up to 4 Kbytes of non-volatile data EEPROM
• 16 x 16-bit working register array
• Three Address Generation Units that enable:
   - Dual data fetch
   - Accumulator write back for DSP operations
• Flexible Addressing modes supporting:
   - Indirect, Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional
   saturation logic
• 17-bit x 17-bit single cycle hardware fractional/
   integer multiplier
• Single cycle Multiply-Accumulate (MAC)
   operation
• 40-stage Barrel Shifter
• Up to 30 MIPs operation:
   - DC to 40 MHz external clock input
   - 4 MHz-10 MHz oscillator input with
      PLL active (4x, 8x, 16x)
• Up to 41 interrupt sources:
   - 8 user selectable priority levels
• Vector table with up to 62 vectors:
   - 54 interrupt vectors
   - 8 processor exceptions and software traps