DEVICE OVERVIEW
This document contains device-specific information for the dsPIC33EVXXXGM00X/10X family Digital Signal Controller (DSC) devices.
dsPIC33EVXXXGM00X/10X family devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit MCU architecture.
Figure 1-1 shows a general block diagram of the core and peripheral modules. Table 1-1 lists the functions of the various pins shown in the pinout diagrams.

Note 1: This data sheet summarizes the features of the dsPIC33EVXXXGM00X/10X family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
      2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.
 
Operating Conditions
• 4.5V to 5.5V, -40°C to +85°C, DC to 70 MIPS
• 4.5V to 5.5V, -40°C to +125°C, DC to 60 MIPS
• 4.5V to 5.5V, -40°C to +150°C, DC to 40 MIPS

Core: 16-Bit dsPIC33E CPU
• Code-Efficient (C and Assembly) Architecture
• 16-Bit Wide Data Path
• Two 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign MUL plus Hardware Divide
• 32-Bit Multiply Support
• Intermediate Security for Memory:
   - Provides a Boot Flash Segment in addition to the existing General Flash Segment
• Error Code Correction (ECC) for Flash
• Added Two Alternate Register Sets for Fast Context Switching

Clock Management
• Internal, 15% Low-Power RC (LPRC) – 32 kHz
• Internal, 1% Fast RC (FRC) – 7.37 MHz
• Internal, 10% Backup FRC (BFRC) – 7.37 MHz
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Additional FSCM Source (BFRC), Intended to Provide a Clock Fail Switch Source for the System Clock
• Independent Watchdog Timer (WDT)
• System Windowed Watchdog Timer (DMT)
• Fast Wake-up and Start-up

Power Management
• Low-Power Management modes (Sleep, Idle and Doze)
• Power Consumption Minimized Executing NOP String
• Integrated Power-on Reset (POR) and Brown-out Reset (BOR)
• 0.5 mA/MHz Dynamic Current (typical)
• 50 µA at +25°C IPD Current (typical)

PWM
• Up to Six Pulse-Width Modulation (PWM) Outputs (three generators)
• Primary Master Time Base Inputs allow Time Base Synchronization from Internal/External Sources
• Dead Time for Rising and Falling Edges
• 7.14 ns PWM Resolution
• PWM Support for:
   - DC/DC, AC/DC, inverters, Power Factor Correction (PFC) and lighting
   - Brushless Direct Current (BLDC), Permanent Magnet Synchronous Motor (PMSM), AC Induction Motor (ACIM), Switched Reluctance Motor (SRM)
   - Programmable Fault inputs
   - Flexible trigger configurations for Analog-to-Digital conversion
   - Supports PWM lock, PWM output chopping and dynamic phase shifting

Advanced Analog Features
• ADC module:
   - Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H
   - Up to 36 analog inputs
• Flexible and Independent ADC Trigger Sources
• Up to Four Op Amp/Comparators with Direct Connection to the ADC module:
   - Additional dedicated comparator and 7-bit Digital-to-Analog Converter (DAC)
   - Two comparator voltage reference outputs
   - Programmable references with 128 voltage points
   - Programmable blanking and filtering
• Charge Time Measurement Unit (CTMU):
   - Supports mTouch® capacitive touch sensing
   - Provides high-resolution time measurement (1 ns)
   - On-chip temperature measurement
   - Temperature sensor diode
   - Nine sources of edge input triggers (CTED1, CTED2, OCPWM, TMR1, SYSCLK, OSCLK, FRC, BFRC and LPRC)