GENERAL DESCRIPTION
The Device is a 128Mx8bit with spare 4Mx8bit capacity. The device is offered in 1.8V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells. A program operation allows to write the 2,112-Byte page in typical 300us and an erase operation can be performed in typical 4ms on a 128K-Byte for X8 device block.

FEATURES
• Voltage Supply: 1.8V (1.7 V ~ 1.95V)
• Organization
   x8:
   - Memory Cell Array: (128M + 4M) x 8bit
   - Data Register: (2K + 64) x 8bit
   x16:
   - Memory Cell Array: (64M + 2M) x 16bit
   - Data Register: (1K + 32) x 16bit
• Automatic Program and Erase
   x8:
   - Page Program: (2K + 64) Byte
   - Block Erase: (128K + 4K) Byte
   x16:
   - Page Program: (1K + 32) Word
   - Block Erase: (64K + 2K) Word
• Page Read Operation
   x8
   - Page Size: (2K + 64) Byte (x8)
   - Random Read: 25us (Max.)
   - Serial Access: 45ns (Min.)
   x16
   -Page Size: (1K + 32) Word (x16)
• Memory Cell: 1bit/Memory Cell
• Fast Write Cycle Time
   x8
   - Program time: 300us (Typ.)
   - Block Erase time: 4ms (Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
   - Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating Gate Technology
   - ECC Requirement: x8 – 1bit/512Byte,
                                     x16 – 1bit/256Word
   - Endurance: 60K Program/Erase Cycles
   - Data Retention: 10 Years
• Command Register Operation
• Automatic Page 0 Read at Power-Up Option
   - Boot from NAND support
   - Automatic Memory Download
• NOP: 4 cycles
• Cache Program/Read Operation for High Performance
   Program
• Cache Read Operation
• Copy-Back Operation
• EDO mode
• Bad-Block-Protect
• One Time Program (OTP) Operation