GENERAL DESCRIPTION
The device has two 2176-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block unit (128Kbytes + 8Kbytes).
The device is a memory device which utilizes the I/O pins for both address and data input/output as well as command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid state file storage, voice recording, image file memory for still cameras and other systems which require high density non-volatile memory data storage.

FEATURES
◾ Voltage Supply
   ― VCC: 3.3V (2.7 V ~ 3.6V)
◾ Organization
   ― Page Size: (2K + 128) bytes
   ― Data Register: (2K + 128) bytes
   ― Block Size: 64Pages = (128K + 8K) bytes
   ― Number of Block per Die (LUN)= 2048
◾ Automatic Program and Erase
   ― Page Program: (2K + 128) bytes
   ― Block Erase: (128K + 8K) bytes
◾ Page Read Operation
   ― Random Read: 25us (Max.)
   ― Read Cycle: 25ns
◾ Write Cycle Time
   ― Page Program Time: 400us (Typ.)
                                          700us (Max.)
   ― Block Erase Time: 3 ms (Typ.)
                                     10ms (Max.)
◾ 1bit/cell
◾ Command/Address/Data Multiplexed DQ Port
◾ Hardware Data Protection
   ― Program/Erase Lockout During Power Transitions
◾ Reliable CMOS Floating Gate Technology
   ― ECC Requirement: 8bit / 512Byte
   ― Endurance: 50K-P/E Cycle Times
   ― Data Retention: 10year
◾ Command Register Operation
◾ Number of partial program cycles in the same page (NOP) : 4
◾ Automatic Page 0 Read at Power-Up Option
   ― Boot from NAND support
   ― Automatic Memory Download
◾ Cache Program Operation for High Performance Program
◾ Cache Read Operation
◾ Copy-Back Operation
◾ Two-Plane Operation
◾ EDO mode
◾ Page copy