Functional Description
Applications
The GS88218/36B is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

FEATUREs
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect Selectable
• IEEE 1149.1 JTAG Compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive strength
• x16/x32 mode with on-chip parity encoding and error detection
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 119-bump BGA package