General Description
The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.

FEATUREs
■ Bidirectional interface between GTLP and LVTTL logic levels
■ Variable Edge Rate Control pin to select desired edge
   rate on the GTLP backplane (VERC)
■ Partitioned as two 8-Bit transceivers with individual latch
   timing and output control but with a common clock.
■ Power up/down high impedance for live insertion.
■ External pin to pre-condition I/O GTLP and LVTTL logic levels
■ Bus-hold data inputs on the A-Port eliminates the need
   for external pull-up resistors on unused inputs
■ LVTTL compatible driver and control inputs
■ Flow through pinout optimizes PCB layout
■ Open drain on GTLP to support wired-or connection
■ A Port source/sink −24 mA/+24 mA
■ B Port sink +100mA
■ D-type flip-flop, latch and transparent data paths
■ −40°C to 85°C Temperature capability
■ Available in TSSOP