Description
Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, without disturbing the outputs. By repeating this process, the output pulse period (Q High, Q Low) can be made as long as desired. Alternatively, a delay period can be terminated at any time by a Low signal on CD, which also inhibits triggering.

FEATUREs
• Outputs Source/Sink 24 mA
• Ordering Information