datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga
HOME  >>>  Siemens AG  >>> HYB314175BJ-50- PDF

HYB314175BJ-50- Hoja de datos - Siemens AG

HYB314175BJ-50 image

Número de pieza
HYB314175BJ-50-

Other PDF
  no available.

PDF
DOWNLOAD     

page
24 Pages

File Size
1.1 MB

Fabricante
Siemens
Siemens AG Siemens

3.3V 256 K x 16-Bit EDO-DRAM
3.3V 256 K x 16-Bit EDO-DRAM
(Low power version with Self Refresh)

The HYB 314175BJ/BJL is the new generation dynamic RAM organized as 262 144 words by 16-bit. The HYB 314175BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 314175BJ/BJL to be packed in a standard plastic 400mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include Self Refresh (L-Version), single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance logic device families.

Preliminary Information
• 262 144 words by 16-bit organization
• 0 to 70 °C operating temperature
• Fast access and cycle time
• RAS access time:
   50 ns (-50 version)
   55 ns (-55 version)
   60 ns (-60 version)
• CAS access time:
   13ns (-50 & -55 version)
   15 ns (-60 version)
• Cycle time:
   89 ns (-50 version)
   94 ns (-55 version)
   104 ns (-60 version)
• Hype page mode (EDO) cycle time
   20 ns (-50 & -55 version)
   25 ns (-60 version)
• High data rate
   50 MHz (-50 & -55 version)
   40 MHz (-60 version)
• Single + 3.3 V (±0.3 V) supply with a builtin VBB generator
• Low Power dissipation
   max. 450 mW active (-50 version)
   max. 432 mW active (-55 version)
   max. 378 mW active (-60 version)
• Standby power dissipation
   7.2 mW standby (TTL)
   3.6 mW max. standby (CMOS)
   0.72 mW max. standby (CMOS) for
   Low Power Version
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify write, CASbefore-RAS refresh, RAS-only refresh, hidden-refresh and hyper page (EDO) mode capability
• 2 CAS / 1 WE control
• Self Refresh (L-Version)
• All inputs and outputs TTL-compatible
• 512 refresh cycles / 16 ms
• 512 refresh cycles / 128 ms
   Low Power Version only
• Plastic Packages:
   P-SOJ-40-1 400mil width

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

Número de pieza
componentes Descripción
PDF
Fabricante
3.3V 256 K x 16-Bit Dynamic RAM 3.3V Low Power 256 K x 16-Bit Dynamic RAM with Self Refresh
Ver
Siemens AG
16 M EDO DRAM (4-Mword x 4-bit) 4 k Refresh/2 k Refresh
Ver
Hitachi -> Renesas Electronics
3.3V 256K X 16 CMOS DRAM (EDO)
Ver
Alliance Semiconductor
256K X 16 BIT EDO DRAM
Ver
Utron Technology Inc
3.3V 8M × 64-Bit EDO-DRAM Module 3.3V 8M x 72-Bit EDO-DRAM Module
Ver
Siemens AG
3.3V 8M × 64-Bit EDO-DRAM Module 3.3V 8M x 72-Bit EDO-DRAM Module
Ver
Infineon Technologies
3.3V 2M × 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module
Ver
Siemens AG
3.3V 4M × 64-Bit EDO-DRAM Module 3.3V 4M x 72-Bit EDO-DRAM Module
Ver
Siemens AG
3.3V 1M × 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
Ver
Siemens AG
3.3V 16M × 64-Bit EDO-DRAM Module 3.3V 16M x 72-Bit EDO-DRAM Module
Ver
Siemens AG

Share Link: GO URL

EnglishEnglish Korean한국어 Chinese简体中文 Japanese日本語 Russianрусский

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]