The device is comprised of eight edge-triggered D-Type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.
A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and VCC range
• TRI-STATE buffer-type outputs drive bus lines directly