GENERAL DESCRIPTION
The IS82C600 TrailBlazer simplifies high-speed system design and layout, providing an SRAM with zero wait-state performance up to 90 MHz, address coding, and “Ready” logic. In many cases, TrailBlazer allows existing system designs to be easily upgraded, enabling the re-use of already available ASICs and glue logic.

FEATURES
• Zero wait-state performance on the Primary Bus
   — Point-to-point interface between the SRAM and the high-speed processor
• Seamless interface to Texas Instruments’ TMS320LC54x high-speed processor
• Integrates the single-ported SRAM with a dualported interface and handshake
   — 9 ns access time to the SRAM
   — Can also be used as a standalone, highspeed SRAM
• Integrates the port-to-port bridge function
   — Broadcasts all processor cycles from Primary Bus to the Secondary Bus
   — Programmability to only broadcast non-SRAM cycles to the Secondary Bus
   — Supports older, slower peripheral devices on the Secondary Bus
   — Allows the processor transparent access to the devices on the Secondary Bus through XCVR pin
   — Supports a Boot ROM on the Secondary Bus
• Features Address Decoding and Ready Logic
   — A total of six Chip Selects
   — Supports “Ready” logic signal generation for memory and I/O
   — Eliminates PALs for address decoding and ready logic
   — No “glue logic” interface for local peripherals on the Secondary Bus processor
• Allows dynamic re-allocation of memory spaces for transparent block moves
   — Programmable memory decoding allows memory blocks to be accessed as either Program Space (PS) or Data Space (DS)
   — Programmable registers to map the internal SRAM memory and external secondary port devices into Data Space (DS), Program Space (PS) and I/O Space (IS)
• Can also be used as a standalone, high-speed SRAM
• Allows the shadowing of the ROM on the Secondary Bus into the on-board SRAM