General Description
KK16C554 is an enhanced quadruple version of the 16C550 UART (Universal Asynchronous Receiver Transmitter). Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead. In this mode, internal FIFOs are activated and 16 bytes plus 3 bit of error data per byte can be stored in both receive and transmit modes.
Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. The Status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions such as parity, overrun, framing, and break interrupt.

FEATUREs
● In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte FIFO to reduce the number of interrupts to CPU.
● Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data.
● Holding Register and Shift Register eliminate need for precise synchronization between the CPU and serial data.
● Independently controlled transmit, receive, line status and data interrupts.
● Programmable Baud Rate Generators which allow division of any input reference clock by 1 to 216-1 and generate an internal 16X clock.
● Independent receiver clock input
● Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#).
● Fully programmable serial interface characteristics.
   - 5-, 6-, 7-, or 8-bit characters
   - Even-, Odd-, or No-Parity bit
   - 1-, 1.5-, 2-Stop bit generation. ( Like other general UARTs, 
      KK16C554 checks only one stop bit, no matter how many they are)
● False start bit detection
● Generates or Detects Line Break
● Internal diagnostic capabilities : Loop-back controls for communications link fault isolation.
● Full prioritized interrupt system controls