The KS8695 “Multi-Port Gateway-on-a-Chip” delivers a new level of networking integration and performance for speeding broadband gateway development.

FEATUREs
• The CENTAUR KS8695 featuring XceleRouter™ Technology, is a single-chip Multi-Port Gateway-on-aChip with all the key components integrated for a highperformance and low-cost broadband gateway
• ARM922T high-performance CPU core
    - 185 MIPS ARM922T core at 166MHz
    - 8kB I-cache and 8kB D-cache
    - Memory Management Unit (MMU) for Linux
    - 32-bit ARM and 16-bit Thumb instruction sets
• XceleRouter™ Technology
    - TCP/UDP/IP packet header checksum generation to offload CPU tasks
    - IPv4 packet filtering on checksum errors
    - Automatic error packet discard
• Integrated switch engine & transceivers:
    - Five 10/100 transceivers and MACs (1P for WAN interface, 4P for LAN switching)
    - 100Base-Tx, 10Base-T and 100Base-Fx modes (Fx in the WAN port).
    - On-chip SRAM as frame buffer memory
    - Wire-speed switching
    - VLAN ID and 802.1p tag/untag options
    - Extensive MIB counter management support
    - IGMP snooping for multicast packet filtering
    - Port-based VLAN
    - QoS/CoS packet prioritization support: per-port, 802.1p and DiffServ based
    - 802.1d spanning tree protocol
    - Dedicated 1K-entry look-up engine
    - Automatic MDI/MDIX crossover on all ports
    - Port mirroring/monitoring/sniffing
    - Broadcast storm protection with % control
    - Full and half-duplex flow control
• Memory and external I/O interfaces
    - 8/16/32-bit wide shared data path for SDRAM, ROM/ SRAM/flash & external I/O
    - Total memory space up to 64MB
    - Intel/AMD-type flash support
• WAN/LAN/EMAC DMA Engines & FIFO
    - DMA engine with burst mode support for efficient WAN, LAN and EMAC data transfers
    - FIFOs for back-to-back packet transfers
• Peripheral Support
    - One MII interface (MAC or PHY mode)
    - 8/16/32-bit external I/O interface supporting PCMCIA or generic CPU/DSP host I/F
    - Eight general-purpose input/output (GPIO)
    - Two 32-bit timer counters (one watchdog)
    - Interrupt controller
    - ARM922T JTAG debug interface
• Power management
    - Reduced CPU and system clock speeds
• System design
    - 208-pin PQFP package
    - Up to 166MHz CPU and 125MHz bus speed
• Reference HW/SW evaluation kit
    - Hardware evaluation board (passes class B EMI)
    - Board support package including firmware source codes, Linux kernel, software stacks
    - Documentation for design & programming

APPLICATIONs
• Multi-port broadband gateway
• Multi-port firewall & VPN appliances
• Combo wireless and wireline gateway
• Multi-port VoIP gateway
• Fiber-to-the-Home managed CPE