Low-Voltage 1:5 Dual Diff. LVECL/LVPECL/LVEPECL/HSTL Clock Driver

The MC100LVEP210 is a low skew 1–to–5 dual differential driver, designed with clock distribution in mind. The LVECL/LVPECL input signals can be either differential or single–ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in LVPECL mode.
The LVEP210 specifically guarantees low output–to–output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot.

• 100ps Part–to–Part Skew
• 35ps Output–to–Output Skew
• Differential Design
• VBB Output
• 475ps Typical Propagation Delay
• High Bandwidth to 1.5GHz Typical
• LVPECL and HSTL mode: 2.375V to 3.8V VCC with VEE = 0V
• LVECL mode: 0V VCC with VEE = –2.375V to –3.8V
• Internal Input Resistors: Pulldown on D, D
• Pullup and Pulldown on CLK
• ESD Protection: >2KV HBM, >100V MM
• Moisture Sensitivity Level 2
    For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34
• Transistor Count = 461 devices