The MCM64PD32 (256K) and MCM64PD64 (512K) are designed to provide a burstable, high performance, L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton II chip set. The MCM64PD32 is configured as 32K x 64 bits and the MCM64PD64 is configured as 64K x 64 bits. Both are packaged in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K x 32 BurstRAMs and two Motorola 3.3 V 32K x 8 FSRAM for the tag RAM.

• Pentium–Style Burst Counter on Chip
• Pipelined Data Out
• 160 Pin Card Edge Module
• Address Pipeline Supported by ADSP Disabled with Ex
• All Cache Data and Tag I/Os are TTL Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rate: 66 MHz
• Fast SRAM Access Times:15 ns for Tag RAM 8 ns for Data RAMs
• One–cycle Deselect Data RAMs
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground Planes
• Single 3.3 V +10%, – 5% Power Supply
• Burndy Connector, Part Number: CELP2X80SC3Z48
• Intel COAST 3.0 Option III Compliant
• Burst Order Select (BOSEL) Option