Introduction
The MMC2114, MMC2113, and MMC2112 are members of a family of general-purpose microcontrollers (MCU) based on the M•CORE M210 central processor unit (CPU).
These are low-voltage devices that operate between 2.7 volts and 3.6 volts. They are well suited for use in battery-powered applications. The maximum operating frequency is 33 MHz over a temperature range of –40°C to 85°C.
   
Features
Features include:
• M•CORE M210 integer processor:
    – 32-bit reduced instruction set computer (RISC) architecture
    – Low power and high performance
• OnCE debug support
• 128 Kbytes (MMC2113) or 256 Kbytes (MMC2114) FLASH
    memory(1):
    – Single cycle byte, half-word (16-bit) and word (32-bit) reads
    – Fast automated program and erase cycles
    – Ability to program one FLASH bank while executing from
        another (MMC2114 only)
    – Interrupt on program/erase command completion
    – Flexible protection scheme for accidental program/erase
    – Access restriction controls for both supervisor/user and
        data/program spaces   
    – Enhanced security feature prevents unauthorized access to
        contents of FLASH (protects company IP)
    – Single supply operation (no need for separate, high voltage
    program/erase supply)
• 8 Kbytes (MMC2113) or 32 Kbytes (MMC2112 and MMC2114) of
    static random-access memory (SRAM):
    – Single cycle byte, half-word (16-bit), and word (32-bit) reads
        and writes
    – Standby power supply support
• Serial peripheral interface (SPI):
    – Master mode and slave mode
    – Wired-OR mode
    – Slave select output
    – Mode fault error flag with CPU interrupt capability
    – Double-buffered receiver
    – Serial clock with programmable polarity and phase
    – Control of SPI operation during wait mode
    – Reduced drive control
    – General-purpose input/output (I/O) capability
• Two serial communications interfaces (SCI):
    – Full-duplex operation
    – Standard mark/space non-return-to-zero (NRZ) format
    – 13-bit baud rate prescaler
    – Programmable 8-bit or 9-bit data format
    – Separately enabled transmitter and receiver
    – Separate receiver and transmitter CPU interrupt requests
    – Two receiver wakeup methods (idle line and address mark)
    – Receiver framing error detection
    – Hardware parity checking
    – 1/16 bit-time noise detection
    – Reduced drive control
    – General-purpose I/O capability
• Two timers:
    – Four 16-bit input capture/output compare channels
    – 16-bit architecture
    – 16-bit pulse accumulator
    – Pulse widths variable from microseconds to seconds
    – Eight selectable prescalers
    – Toggle-on-overflow feature for pulse-width modulation
• Queued analog-to-digital converter (QADC):
    – Eight analog input channels
    – 10-bit resolution ±2 counts accuracy
    – Minimum 7 µs conversion time
    – Internal sample and hold
    – Programmable input sample time for various source
        impedances
    – Two conversion command queues with a total of 64 entries
    – Subqueues possible using pause mechanism
    – Queue complete and pause interrupts available on both
        queues
    – Queue pointers indicate current location for each queue
    – Automated queue modes initiated by:
        External edge trigger and gated trigger
        Periodic/interval timer, within queued analog-to-digital
            converter (QADC) module {queue1 and queue2}
        Software command
    – Single-scan or continuous-scan of queues
    – Output data readable in three formats:
        Right-justified unsigned
        Left-justified signed
        Left-justified unsigned
    – Unused analog channels can be used as digital I/O
    – Minimum pin set configuration implemented (Continue ...)